The present invention relates generally to computer graphics, and more specifically to improvements in a display controller architecture which improves readback bandwidth of sequential access to display data memory.
The last several years have seen an evolution in the IBM-compatible personal computer field as the once heralded original PC has given way to models referred to as the XT and the AT, and current models based on Intel's 80386 and 80486 microprocessors. Software developed for use with systems now available increases the demand on display controllers. Consumer demand for increased resolution, an improved color palette, and faster raster scans to improve the ergonomics of the graphic user interface has added to the pressure on display control systems.
FIG. 1 shows a prior art computer system 100 which is capable of video graphic display. The computer system comprises a CPU 110, a system memory 112, and a display system 102. The display system comprises a display controller 116, a display memory 124, and a display device such as a CRT monitor (or CRT) 120. Clearly, references to a CRT should be taken to include other display devices such as LCD flat panel displays and the like. CPU 110 generates data to be drawn into a particular pixel location on CRT 120 of display system 102. This can be done by transferring actual pixel data or by transferring instructions to special drawing circuitry in the display controller.
Display memory 124 can be viewed as a single memory. Given current technology at the time the parent to this application was filed, the memory is typically implemented as a plurality of memory chips. For example, a 1-MByte memory is often implemented using two 256K.times.16 (bit) memory chips. Whether the memory is implemented as a single chip or a plurality of chips, it is often referred to as a memory array.
Data to be drawn is stored in display memory 124 until it is sequentially accessed by display controller 116 for output onto the CRT. Upon CPU initialization, data is transferred from system memory 112 to display controller 116 along a data bus 114, and from display controller 116 to display memory 124 along a display memory data bus 122. Data displayed on the CRT is transferred from display memory 124 to the display controller 116 along display memory data bus 122, and from display controller 116 to CRT 120 on a CRT bus 118. Thus, data paths from CPU 110 (or portions of the display controller) to display memory 124 and from display memory 124 to the CRT 120 both transfer data on display memory bus 122. The display controller arbitrates between the two types of data transfers (CPU 110 to display memory 124, and display memory 124 to CRT 120). The screen refresh (reads from display memory) must take precedence over updating display memory (writes to display memory) since the screen must be refreshed at fixed intervals.
The evolution of video display systems towards increased resolution, improved color palette, and faster raster display increases the demand on the system. Increasing the number of colors available on the screen increases the number of bits per pixel. Increased system resolution increases the amount of data transferred since the number of pixels per screen is increased. For example, for resolutions of 1024.times.768 pixels with 8 bits per pixel, the display memory is over 5 times the size as for the standard 640.times.480 pixels with 4 bits per pixel. Thus, over 5 times the amount of data is transferred to the CRT.
As the resolution increases, the number of data transfers from CPU 110 to display memory 124 (on buses 114 and 122) and from display memory 124 to CRT 120 (on buses 122 and 118) increases. In addition, as the display refresh rate increases data transfers from display memory 124 to the CRT 120 increase. This increases the number of accesses on both the display memory bus 122 and CRT bus 118.
The bandwidth of display memory 124 (number of data accesses per second) is limited by the physical characteristics of the display memory. The number of data accesses to display memory 124 is typically in the range of 100 Mbytes per second. As noted above, refreshing the CRT has priority over CPU 110 to display memory 124 transfers. Thus, accesses from display memory 124 to the CRT 120 decrease the amount of time available to CPU 110 for access to the display memory 124 for CPU to display memory transfers. With increased resolution, color depth and refresh rates, the CPU must wait longer for access to display memory 124 on display memory bus 122.
FIG. 2 is a graphical representation illustrating the decreased CPU access available as the resolution increases. The x-axis indicates the resolution given a constant refresh rate and color depth; the y-axis indicates the bandwidth in bytes per second. Line 210 indicates the constant maximum bandwidth of display memory. Line 212 shows the amount of access time required for display memory to CRT transfers at a given resolution. The distance 214 under curve 212 is the bandwidth used for display memory to CRT transfers at a particular resolution. The distance 216 is the bandwidth available for CPU to display memory data transfers.
From FIG. 2, it can clearly be seen that as the resolution of the display increases, the amount of time available for the CPU decreases. Since priority must be given to refreshing the display, there is a delay in updating the display memory. From the user's point of view, the supposedly fast computer is sluggish and unresponsive.
One method of avoiding problems of contention between the CPU and the CRT for control of the display memory bus is to use a VRAM (Video RAM). FIG. 3 is a block diagram of a prior art display system 300 using a VRAM 310 to store display data. The display system comprises a VRAM 310, a display controller 316, a CRT monitor 320, a CPU 322 and a system memory 324.
Unlike the conventional DRAM 124 shown in the system illustrated in FIG. 1, VRAM 310 has two paths between display controller 316 and display memory 310. The first data path is a bidirectional bus 312 used solely for CPU 322 to display memory 310 data transfers. The second path is a unidirectional serial data bus 314 used only for display memory 310 to CRT 320 transfers. The serial port of VRAM 310 exploits the nature of the video display system 300 since data transferred from display memory 310 to the CRT 320 is transferred to the CRT 320 from contiguous memory locations. Although by providing dual data buses the VRAM avoids the problem of data contention with almost no overhead to the bandwidth, a VRAM is much more expensive than a conventional DRAM. An inexpensive display system for increasing bandwidth allocation on a display memory bus is needed.